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Honored Contributor
Honored ContributorVHDL help, frequency Division
I need some help coding a 25 bit frequency divider. I seriously just cant figure it out. I had to design a digital clock with a mod 6 and mod 10 counter. everything seems to be fine, but ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- As I said before, I'll let someone else help you with actually doing the frequency division. You could try a simulation in Quartus to see whether the code you wrote produces the intended behavior. For a course assignment, the cautions I referred you to might not matter to get something working well enough in the lab. The more reliable the solution has to be, the more those considerations matter any time you drive a clock used internal to the FPGA with logic resources as you would be doing if you drive it with a frequency divider. --- Quote End --- wah wah wah :(
