Verilog delay modelling

is that what you want?

by the way sim_tq is simulation base project.

//--------------------------------------------------------------------

`timescale 1ns/1ns

module tq ( input a, output reg b);

always @ ( * )

begin

b <=# 5 a;

end

endmodule

module sim_tq;

reg a;

initial

fork

# 0 a = 1;

# 105 a = 0;

# 200 a = 1;

join

tq obj

(

.a(a),

.b()

);

endmodule

//--------------------------------------------------------------------