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Honored Contributor
Honored ContributorVerilog: Concept on Blocking assignment and always
i read an article about blocking assignment. module fbosc1 (y1, y2, clk, rst); output y1, y2; input clk, rst; reg y1, y2; always @(posedge clk or posedge rst) if (rst) y1 = 0; // r...
Altera_ForumHonored Contributor
Honored ContributorIt is correct that the article i read is Cumming's SNUG-2000 paper nonblocking assignments in verilog synthesis, coding styles that kill!
Jakobjones, ur explaination helps me a lot,thanks
