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Honored Contributor
Honored ContributorVerilog: Concept on Blocking assignment and always
i read an article about blocking assignment. module fbosc1 (y1, y2, clk, rst); output y1, y2; input clk, rst; reg y1, y2; always @(posedge clk or posedge rst) if (rst) y1 = 0; // r...
Altera_ForumHonored Contributor
Honored ContributorThe same example is used in Cliff Cummings' Verilog courses (Sunburst Design). It's possible the poster grabbed the example from one of those courses.
For example, page 9-4 of the Expert Verilog-2001 course Rev. 200701 uses it. Jake
