Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorVerilog: Concept on Blocking assignment and always
i read an article about blocking assignment. module fbosc1 (y1, y2, clk, rst); output y1, y2; input clk, rst; reg y1, y2; always @(posedge clk or posedge rst) if (rst) y1 = 0; // r...
Altera_ForumHonored Contributor
Honored ContributorThe above example is apparently taken from Cumming's SNUG-2000 paper nonblocking assignments in verilog synthesis, coding styles that kill!
Because it has much more explanation and additional cases, it's good to mention the original source. http://csg.csail.mit.edu/6.375/papers/cummings-nonblocking-snug99.pdf
