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Altera_Forum
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14 years ago

Verilog Compilation Problem: All available logic elements used!

Hi all, I am having a problem compiling my verilog code in Quartus II where all the available logic elements (12'060) are used by the compiler. The code (excerpt) is as follows: begin...
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Altera_Forum
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14 years ago

The shown code excerpt is effectively meaningless, because the design functions causing the large resource utilization are obviously outside this text.

By commenting the said lines, you force some signals to constant values, which in turn disables the code depending on these signals. A synthesis compiler is very clever in omitting any unused logic.