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Altera_Forum's avatar
Altera_Forum
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14 years ago

Verilog code to block diagram

Hello Folks, I am very new to FPGAs/CPLDs so sorry if I'm asking something trivial but I am digging around the net for days now finding the answer to my problem. Unfortunately I couldn't find a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

  • Keep opened this verilog file in quartus and go to

--- Quote Start ---

file-->create/update-->create symbol files for current file

--- Quote End ---

  • Symbol file will be " <you current file name> . bsf".Then you can add with other blocks for connections.

  • You will get lines named "Enabled, Clock_In" at input side and "PulseS, PulseR" output side of the block.