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Altera_Forum
Honored Contributor
Honored Contributorverilog code help!!
configuration cfg_sine_wave_tb of sine_wave_tb is for bench for uut: sine_wave use entity work.sine_wave(arch1); end for; end for; end cfg_sine_wave_tb; this code ...
Altera_ForumHonored Contributor
Honored ContributorThis isn't Verilog, it's VHDL.
In VHDL you can define several architectures for the same block, for example a RTL architecture for synthesis and a functional one for test benches. The VHDL configuration block is used to tell the simulator what architecture to use. You can find more information about VHDL configurations here (http://www.doulos.com/knowhow/vhdl_designers_guide/configurations_part_1/)
