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Altera_Forum's avatar
Altera_Forum
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15 years ago

Verilog code errors???

Hi, I have this piece of code which when compiled with Quartus II web free resulting in errors (follow comment //). Please advise how to fix them. Thanks. 1) assign Sclk = SCLKout; ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I have another error:

if (Data_Lmt == 0)

begin

CS1reg <= 1'b1;

CS2reg <= 1'b1;

Databus <= SPIdata_reg; // Error (10137): Verilog HDL Procedural Assignment error at spi_intf.v(161): object "Databus" on left-hand side of assignment must have a variable data type

BUSY <= 1'b0;

Comm_RW_state <= SPI_RW_Statmachine_Read_repeat;

end

Declaration: databus is inout type of 8bits, SPIdata_reg is type reg of 8bits

Please advise. Thanks.