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Altera_Forum's avatar
Altera_Forum
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15 years ago

Verilog code errors???

Hi, I have this piece of code which when compiled with Quartus II web free resulting in errors (follow comment //). Please advise how to fix them. Thanks. 1) assign Sclk = SCLKout; ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

assign# 500 rstb = 1'b0; 1'b1;

Two comments:

- As shown, it's no legal Verilog syntax

- Verilog (as well as VHDL) delay statements are simply ignored in synthesis