Varible clock rate

I am currently not good at reading verilog but let me suggest my algorithm in vhdl:

signal accum : unsigned(32 downto 0) := (others => '0');
-- on a clked process
accum <= accum(31 downto 0) + increment;
end process;
 
enable <= accum(32);

The main idea is adding 31:0 to 32:0 freely as this wraps up the result back and so the overflow should be one pulse. Please let me know if it works. Remember all your clked staements and clked components must have clk enable added to them.