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Not quite right. Software SERDES (Cyclone series) uses DDR registers for all deserialization factors, hardware SERDES (Stratix, Arria) doesn't use it at all.
The original question isn't still clear to me. Normally you would supply a frame (slow) clock rather than a bit (fast) clock to a SERDES block, the fast clock is generated internally. So the difference between SDR and DDR is just an internal detail of the SERDES, which you don't have to care for.
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The original question was, if the input for ALTLVDS_RX is in DDR format, what is the output format ? is it in SDR or DDR?
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