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Altera_Forum
Honored Contributor
Honored ContributorUsing the ALTLVDS_RX DDR in = DDR out?
Hi, Can anyone tell me that by using ALTLVDS_RX core provided by Altera, and if i use deserialization factor of 6; if the input in DDR format, the output of this block will be in DDR format too...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Not quite right. Software SERDES (Cyclone series) uses DDR registers for all deserialization factors, hardware SERDES (Stratix, Arria) doesn't use it at all. The original question isn't still clear to me. Normally you would supply a frame (slow) clock rather than a bit (fast) clock to a SERDES block, the fast clock is generated internally. So the difference between SDR and DDR is just an internal detail of the SERDES, which you don't have to care for. --- Quote End --- The original question was, if the input for ALTLVDS_RX is in DDR format, what is the output format ? is it in SDR or DDR?
