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Altera_Forum
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9 years ago

Using PLL_L_CLKOUT on a MAX10

Hello, I'm using multiple Max10 devices: 10M02SCU169I7G I would like to use the DIFFIO_RX_L19 to output the PLL CLK (negative = pin M3 and positive is L3). The pin optional functions a...
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Altera_Forum
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9 years ago

DIFFIO_RX outputs don't support true LVDS drivers. You can either switch to LVDS_E_3R, as suggested, or use a DIFFIO_TX_RX pair. In the latter case you also get increased jitter and skew due to non-dedicated clock routing.