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Altera_Forum
Honored Contributor
Honored ContributorUsing CPLD/FPGA as a Timer
Hi. I am interested to implement a timer that can count up to hours, in my FPGA/CPLD. The main purpose of the timer is to issue a pulse after a certain fixed duration, eg. every 2 hours. Normal...
Altera_ForumHonored Contributor
Honored Contributorhow about pre-scaling at the output? say with few ripple-counter ICs and a D-flipflop to square the waveform duty cycle to 50%
sure, a bit of a solder job but it may be easier than tinkering with the 5Mhz especially if you are using pre-fab board with all-SMD parts... ~B
