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Altera_Forum
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18 years ago

Using CPLD/FPGA as a Timer

Hi. I am interested to implement a timer that can count up to hours, in my FPGA/CPLD. The main purpose of the timer is to issue a pulse after a certain fixed duration, eg. every 2 hours. Normal...
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Altera_Forum
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18 years ago

Thanks Frank.

I guess without using a much slower clock, there is no way I can greatly reduce the amount of LEs used.

Regards,

CW