Using Altera Multi-Port Front End (MPFE) with DDR2 Controller (ALTMEMPHY)

Did you already solve this problem?

I'm have the same issue in simulation and hardware..

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Hi,

I am trying to use Altera Multi-Port Front End (MPFE) code available from AN 637: Sharing External Memory Bandwidth Using the Multi-Port Front-End Reference Design. This design is for Stratix V, using Uniphy core are controller for DDR3.

I am using only the MPFE source codes from the above reference design in Cyclone III with ALTMEMPHY DDR2 Controller. Now in my design i am trying to write and read data which is a video frame of 720x576 resolution.I could see that my write side is happening properly, but when i come to read side i find that at times the master-side of the MPFE gives 2 burst_transfer signals for reading from single address. Because of which i see that at the ALTMEMPHY local-side the data is been read from the same address twice.

I had checked MPFE slave side to see whether signals are properly driven; I didn't see any difference. It would be of great help if anyone out here can give me some suggestions on this issue. i am attaching few snap shots of SignalTap for you reference.

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