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Honored Contributor
Honored ContributorUsing ALTCLKCTRL as clock mux with enable
I am using a Stratix III and have 4 clocks being output from a single PLL. What I would like to do is to generate two output clocks by multiplexing clk[0] and clk[2] together for the first output clo...
Altera_ForumHonored Contributor
Honored ContributorWell, after further investigation this seems to be showing up as a known issue in Quartus 9.1sp2, although there has been no mention of it in the subsequent release notes.
altera.com/literature/rn/rn_qts_91sp2.pdf?GSA_pos=1&WT.oss_r=1&WT.oss=Rule%20C101&SRNo=10847143
