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Altera_Forum
Honored Contributor
Honored ContributorUsing ALTCLKCTRL as clock mux with enable
I am using a Stratix III and have 4 clocks being output from a single PLL. What I would like to do is to generate two output clocks by multiplexing clk[0] and clk[2] together for the first output clo...
Altera_ForumHonored Contributor
Honored ContributorNo problem, thanks for the quick reply. It did make me think to double-check Altera's design example on a Stratix III device.
If their own design example shows violations, I suppose it may be worth contacing them directly unless anyone else has run into this issue before?
