Forum Discussion

Honored Contributor

14 years ago

Using ALTCLKCTRL as clock mux with enable

I am using a Stratix III and have 4 clocks being output from a single PLL. What I would like to do is to generate two output clocks by multiplexing clk[0] and clk[2] together for the first output clo...

Altera_Forum

Honored Contributor

14 years ago

No problem, thanks for the quick reply. It did make me think to double-check Altera's design example on a Stratix III device.

If their own design example shows violations, I suppose it may be worth contacing them directly unless anyone else has run into this issue before?

Forum Discussion

Using ALTCLKCTRL as clock mux with enable

Recent Discussions

Cyclone 5 SoC FPGA Bank Supply Prerequisite

AGILEX 5 Migration issue

To INTEL - Request for Compliance Data from Analog Devices, Inc

Arria 10 GX RX max intra-differential pair skew

MAX10 Bitstreams Authentication