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Altera_Forum
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14 years ago

Using ALTCLKCTRL as clock mux with enable

I am using a Stratix III and have 4 clocks being output from a single PLL. What I would like to do is to generate two output clocks by multiplexing clk[0] and clk[2] together for the first output clo...
Altera_Forum's avatar
Altera_Forum
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14 years ago

Yes, that is the megafunction block that I am using, but I can't find anything in there that would explain the warnings I am seeing.

I have downloaded the "global clock buffer" design example mentioned in the user guide and run through Quartus 10.1. While I don't get any design assistant warnings if I target the design to the default Stratix II device, if I change it to a Stratix III I get the same "Gated clock should be implemented according to the Altera standard scheme" critical violation.