--- Quote Start ---
I am uncomfortable with the construction of the following code, specifically the use of a signal both as a clock and as a condition. The signal “irst” is used within the always loop as a clock and within the “if” statement as a test condition. The decisions are synchronous with the specified clocks “<=”. My understanding of the “<=” convention is the value of the signal previous to the occurrence of the corresponding clock is latched at the specified clock edge. I do not see how the condition of “irst” is ever satisfied with the “irst” positive clock. Within the simulation, the value of “irst” is captured. The behavior I see within the simulation is:
irst set high within the “INITIAL” statement, then low after a short time.
SCK begins clocking some time later.
The register array sreg[] is not blank within the simulator window until after the fifth occurrence of SCK. At that time, all the registers appear with a value of “0”.
code sample:
module spi_slave (
CS_N, SCK, SDI, SDO,
irst, iclk, orst
);
…..
parameter NUM_REG = 8;
integer nr;
wire [11:0] rdat = {serial_in[10:0],SDI};
reg [11:0] sreg [1:NUM_REG-1];
always @(posedge irst or posedge SCK) begin // expect data to change on falling SCK
if (irst)
begin
for(nr=1; nr<NUM_REG; nr=nr+1)
sreg[nr] <= 0;
end
else if (&all_cnt[3:0])
begin
sreg[opcode] <= rdat;
end
end
--- Quote End ---
Hi,
did you see a posedge of the reset signal in your simulation ?
Try to start with a "0" for irst.
Kind regards
GPK
Honored Contributor
