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Honored Contributor
Honored ContributorUsing a fifo with clock enable
Hello, I have a design with a main clock of 100 MHz. With a clock divider I made a clock enable for about a 9 MHz (clock). The 9 MHz will be used to control and LCD. The data which needs to be ...
Altera_ForumHonored Contributor
Honored ContributorI would drive the read clock with the 100MHz clock and write some code that would drive a signal high for one 100MHz clock cycle every 11 100MHz clock cycles. Use that signal to drive the rdreq and any other logic that needs to operate at the 9MHz rate. This way you will only get one rdreq and will not lose data.
