User data in the system EEPROM

Yes.

Use the ALTASMI_PARALLEL core to access the EPCS.

Note that you'll have R/W access to the entire EPCS' contents.

--- Quote Start ---

Yes.

Use the ALTASMI_PARALLEL core to access the EPCS.

Note that you'll have R/W access to the entire EPCS' contents.

--- Quote End ---

Thank you!

Excuse me for stupid question - if I have ep3c25 with 25K elements, how much user space in epcs64 I may have? Reading documentation this stuff is not obsious (maybe it is expected that I am very familiar with technology).

Another thing I am wondering about is handbook stating

EP3C25 / 24,624 / 66 / 608,256

And memory in bits 608,256 (approx 78Kbytes) - is this space in the chip dedicated to RAM, or shared with some other logic? I mean if I have some structure coded in the chip, will I still have 78K RAM?

The space taken by configuration depends on weather you're using compression or not.

If you don't use compression, it is fixed for a given FPGA model and you can find it in the device handbook (Table 9-3 in the Cyclone III handbook).

For the EP3C25, it's 5,800,000 bits. Which leaves you with about 60 Mbit left in the EPCS.

If you use compression, then it will change from design to design.

Those memory bits are dedicated to RAM.

The handbook is stating that there are 24,624 Logic Elements plus 66 M9K dedicated RAM blocks

66 * 9K => 608,256

--- Quote Start ---

The space taken by configuration depends on weather you're using compression or not.

If you don't use compression, it is fixed for a given FPGA model and you can find it in the device handbook (Table 9-3 in the Cyclone III handbook).

For the EP3C25, it's 5,800,000 bits. Which leaves you with about 60 Mbit left in the EPCS.

If you use compression, then it will change from design to design.

Those memory bits are dedicated to RAM.

The handbook is stating that there are 24,624 Logic Elements plus 66 M9K dedicated RAM blocks

66 * 9K => 608,256

--- Quote End ---

Cool, thank you so much. I was planning to use several pins to attach to the SEEPROM where user data will be stored - now I see that it is not really needed, will store that in system chip.

Regarding RAM - thank you for clarification.

I assume you already noticed that EPCS flash memory can be only erased in pages. As another point, the Quartus programmer is usually erasing it completely when updating the FPGA configuration, which may be unwanted if you intend to keep calibration data, module identities etc. across FPGA software updates.

There are several possible reasons to prefer an additional I2C or SPI EEPROM for parameter storage.