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Altera_Forum
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13 years ago

use OVL (Open Verification Library) with Quartus II VHDL

Hi hi!! I'm trying to add some assertions to my VHDL design (ex. ovl_always). I got the library from accellera (V2.6), and I just don't know which files should I ADD (Assignments/files/) to my pro...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

vhdl 2008 has a new keyword default which is causing the problem. You could either do what you've done (Im never happy modifying library code like this) or change the code compile language to VHDL 1993.