Forum Discussion

Honored Contributor

15 years ago

Unconstrained inputs/outputs

Hi, I just started to use the TimeQuest Timing Analyzer to constraint a new VHDL design (EP3C16). I managed to constraint my clock and derived clocks. I have a process which is a state mac...

Altera_Forum

Honored Contributor

15 years ago

Have you read also the TQ user guide written by Rysc?

http://alterawiki.com/wiki/timequest_user_guide

I think what you need is explained very clearly here.

Forum Discussion

Unconstrained inputs/outputs

Recent Discussions

Schematics/layout for TerasIC SoCKit rev. D with Cyclone V

which A3C devices have on chip decoupling capacitors

Cyclone IV drop in replacement confirmations

Agilex 3 PLL in Source Synchronous mode ?

Cyclone 10 GX AS x4 Configuration Compatibility with Infineon S25FS512S (Custom Flash Definition)