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Honored Contributor

15 years ago

Unconstrained inputs/outputs

Hi, I just started to use the TimeQuest Timing Analyzer to constraint a new VHDL design (EP3C16). I managed to constraint my clock and derived clocks. I have a process which is a state mac...

Altera_Forum

Honored Contributor

15 years ago

Have you read also the TQ user guide written by Rysc?

http://alterawiki.com/wiki/timequest_user_guide

I think what you need is explained very clearly here.

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Unconstrained inputs/outputs

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