Unable to simulate the testbench in Modesim

Hi,

I have program for an OR gate which I am able to compile successfully in Quartus II. I am trying to simulate the design in Modelsim using RTL simulation. When Modesim opens up only the OR gate design file is displayed in the library and not the test bench. I am not able to simulate/connect the testbench in ModelSim.

I have referred to this thread (http://www.alteraforum.com/forum/showthread.php?t=34391) but I get an error 'C:/altera/15.0/modelsim_ase/win32aloem/vlog failed.'

I am able to simulate the basic andgate program in Modelsim using RTL simulation from Quartus.

Thanks,