New Contributor
Regular ContributorHi,
You have to use create_clock on the input clock port (ADC_1CH_CLKOUT, ADC_2CH_CLKOUT and ENCODE_CLOCK) of your interface that describes the characteristics of the source clock. If the clock and data arrive at FPGA edge-aligned, you can use a PLL to shift the clock used to latch the data. If the clock and data arrive at FPGA center-aligned, you have to specify the clock phase adjustment on the input clock with the waveform options. According to AN 433, the false path and multicycle path exceptions are applied between the virtual clock and data clock. In the sdc, you are constraining the false path and multicycle path between the virtual clock itself (adc1ChClockout and adc2ChClockout).
Thanks.
Best regards,
KhaiY
New ContributorHi Khai,
thank you for your response. There were no virtual clocks in my SDC file because I specified my input delays relative to the ADC clockout with the timings specified in the datasheet. I did this because I also wanted to analyze the timings from data launched by the input receivers and latched by the ENCODE_CLOCK. I don't think that this deviation from the AN433 affects my timing issue. To make sure, I changed the SDC file accordingly:
- Add virtual clocks (data is delayed to clock by typically 0.4 ns)
create_generated_clock -name adc2ChDataClock_virt -source [get_ports {ADC_2CH_CLKOUT}] -offset 0.4 create_generated_clock -name adc1ChDataClock_virt -source [get_ports {ADC_1CH_CLKOUT}] -offset 0.4
- Set the input delays, false paths and multicycle paths relative to the virtual clocks:
set_input_delay -min -clock [get_clocks {adc2ChDataClock_virt}] -0.1 [get_ports ADC_2CH_DATA*] -add_delay set_input_delay -min -clock [get_clocks {adc2ChDataClock_virt}] -0.1 [get_ports ADC_2CH_DATA*] -clock_fall -add_delay set_input_delay -max -clock [get_clocks {adc2ChDataClock_virt}] 0.15 [get_ports ADC_2CH_DATA*] -add_delay set_input_delay -max -clock [get_clocks {adc2ChDataClock_virt}] 0.15 [get_ports ADC_2CH_DATA*] -clock_fall -add_delay set_input_delay -min -clock [get_clocks {adc1ChDataClock_virt}] -0.1 [get_ports ADC_1CH_DATA*] -add_delay set_input_delay -min -clock [get_clocks {adc1ChDataClock_virt}] -0.1 [get_ports ADC_1CH_DATA*] -clock_fall -add_delay set_input_delay -max -clock [get_clocks {adc1ChDataClock_virt}] 0.15 [get_ports ADC_1CH_DATA*] -add_delay set_input_delay -max -clock [get_clocks {adc1ChDataClock_virt}] 0.15 [get_ports ADC_1CH_DATA*] -clock_fall -add_delay set_false_path -setup -fall_from [get_clocks {adc2ChDataClock_virt}] -rise_to [get_clocks {adc2ChClockout}] set_false_path -setup -rise_from [get_clocks {adc2ChDataClock_virt}] -fall_to [get_clocks {adc2ChClockout}] set_false_path -hold -fall_from [get_clocks {adc2ChDataClock_virt}] -fall_to [get_clocks {adc2ChClockout}] set_false_path -hold -rise_from [get_clocks {adc2ChDataClock_virt}] -rise_to [get_clocks {adc2ChClockout}] set_false_path -setup -fall_from [get_clocks {adc1ChDataClock_virt}] -rise_to [get_clocks {adc1ChClockout}] set_false_path -setup -rise_from [get_clocks {adc1ChDataClock_virt}] -fall_to [get_clocks {adc1ChClockout}] set_false_path -hold -fall_from [get_clocks {adc1ChDataClock_virt}] -fall_to [get_clocks {adc1ChClockout}] set_false_path -hold -rise_from [get_clocks {adc1ChDataClock_virt}] -rise_to [get_clocks {adc1ChClockout}] set_multicycle_path -setup -rise_from [get_clocks {adc1ChDataClock_virt}] -rise_to [get_clocks {adc1ChClockout}] 0 set_multicycle_path -setup -fall_from [get_clocks {adc1ChDataClock_virt}] -fall_to [get_clocks {adc1ChClockout}] 0 set_multicycle_path -setup -rise_from [get_clocks {adc1ChDataClock_virt}] -rise_to [get_clocks {adc2ChClockout}] 0 set_multicycle_path -setup -fall_from [get_clocks {adc1ChDataClock_virt}] -fall_to [get_clocks {adc2ChClockout}] 0
- I also had to remove the clock latency because it is not recognized anymore as common clock path pessimism). This is OK for the MWE
#set_clock_latency -source -early -0.3 [get_clocks {adc2ChClockout}] #set_clock_latency -source -late 0.2 [get_clocks {adc2ChClockout}] #set_clock_latency -source -early -0.3 [get_clocks {adc1ChClockout}] #set_clock_latency -source -late 0.2 [get_clocks {adc1ChClockout}]
With these changes, the timing analysis for the capture paths is exactly the same.
