Forum Discussion

New Contributor

7 years ago

Unable to establish a link of RapidIO

When I use RapidIO in Arria 10 to communicate with DSP , I find port_initialized of IP core is high , but the port_ok of the port 0 error and status CSR-offset:0x158 is low. According to RapidIO Gen1...

Nathan_R_Intel

Contributor

7 years ago

Hie Tah, Some of the reasons for cannot establish link is already provided in the Intel FPGA Wiki section below such as link partner does not match core configuration, core in reset, timing no met, incorrect analogue settings etc. https://fpgawiki.intel.com/wiki/RapidIO_Gen1_Debug_Checklist#Unable_to_establish_a_link Hence, please check the other checklist questions related to link cannot establish. Regards, Nathan

晓郝

New Contributor

7 years ago

hi,

OK, I will check that again.

Thanks.

Forum Discussion

Unable to establish a link of RapidIO

Recent Discussions

Cannot access SSLC portal for Questa License

Why does PTA show zero W for F-tiles in Hierarchical Design Editor

FPGA ECCN Request

AGRW027R28A2I2V Thermal Model

AGMF039R47A1E2V Compact Thermal Model