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Altera_Forum
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14 years ago

Trying to develop my own Cordic core at VHDL.. problems

Hello i am trying to develop my own Cordic core at VHDL.. but i am having some problems. I basically have a block of gain and a block of angles that works like that (just a snap) ... case ind...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Tricky thanks so much for your really good help.

To do a synchronous rom i have to drive the clock signal and my mux will only happen in the clk signal right?

I didnt clock the second process because it's a moore state machine and the 2nd process says it's only sensitive to the state.

How can i solve this lach issue with a moore sm