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Altera_Forum
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15 years ago

Trying to develop my own Cordic core at VHDL.. problems

Hello i am trying to develop my own Cordic core at VHDL.. but i am having some problems. I basically have a block of gain and a block of angles that works like that (just a snap) ... case ind...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

And a 3rd thing - With the atan and ganho_k modules- you appear to have created an asynchronous rom. This is not a very good idea (as all your logic is going to dissapear). You are going to get very very poor Fmax performance.