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Altera_Forum
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14 years ago

Trying to develop my own Cordic core at VHDL.. problems

Hello i am trying to develop my own Cordic core at VHDL.. but i am having some problems. I basically have a block of gain and a block of angles that works like that (just a snap) ... case ind...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Some question immediatly arrise:

Why is pi and pi_2 a signal and not a constant?

Why have you not clocked the second process? the way it is currently, you are going to get a LOT of latches (which are bad) because you have not assigned every signal in every branch. You also have an incomplete sensitivity list (all of the signals that drive other signals MUST be in the sensitivity list, otherwise the firmware will not match the simulation).

For the error - I can only only assume you have assigned angulo_indece more than once.

Basically, there are many many problems with this code.