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I don't quite understand what you're trying to do here. You're doing read-only on the flash (FL_WE_N <= 1) and you're sending data from GPIO_0 to FL_DQ, which won't do anything because you're doing read-only.
Also, why is GPIO_0 bidirectional?
If you're trying to send something out of GPIO_0, GPIO_0 must be on the left hand side of an assignment somewhere.
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That's a bit of what I was confused about. It had looked like in the datasheet for this dev board that GPIO 1 and 2 were both bidirectional, so I figured I needed to implement them as such?
So if i'm understanding you properly, seeing as the FLASH is in read-only mode, it's pins (maybe aside from the control pins) should be set as INPUT in my port list, all driving the GPIO?
So:
library ieee;
use ieee.std_logic_1164.all;
entity mapper is
port(
FL_ADDR : in std_logic_vector(21 downto 0) ;
FL_DQ : in std_logic_vector(7 downto 0) ;
FL_CE_N : out std_logic;
FL_OE_N : out std_logic;
FL_RST_N : out std_logic;
FL_WE_N : out std_logic;
GPIO_0 : out std_logic_vector(35 downto 0)
);
end mapper;
architecture arch of mapper is
begin
--CONTROL LINES
FL_CE_N <= '0';
FL_OE_N <= '0';
FL_RST_N <= '1';
FL_WE_N <= '1';
--DATA LINES
GPIO_0(21 downto 14) <= FL_DQ(7 downto 0) ;
-- ADDRESS LINES
GPIO_0(2) <= FL_ADDR(17);
GPIO_0(24) <= FL_ADDR(16);
GPIO_0(4) <= FL_ADDR(15);
GPIO_0(29) <= FL_ADDR(14);
GPIO_0(28) <= FL_ADDR(13);
GPIO_0(5) <= FL_ADDR(12);
GPIO_0(25) <= FL_ADDR(11);
GPIO_0(23) <= FL_ADDR(10);
GPIO_0(26) <= FL_ADDR(9);
GPIO_0(27) <= FL_ADDR(8);
GPIO_0(6) <= FL_ADDR(7);
GPIO_0(7) <= FL_ADDR(6);
GPIO_0(8) <= FL_ADDR(5);
GPIO_0(9) <= FL_ADDR(4);
GPIO_0(10) <= FL_ADDR(3);
GPIO_0(11) <= FL_ADDR(2);
GPIO_0(12) <= FL_ADDR(1);
GPIO_0(13) <= FL_ADDR(0);
end arch;
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