Transciever channel placement order for PCIe in stratix V

Is it necessary to have transceiver channel placements in-order to use PCIe Hard IP in stratix V FPGA. For instance, for a 8-lane PCIe hard IP endpoint can I place channels in the following order 0,1,3,4,4,5,6,7 instead of 0,1,2,3,4,5,6,7.