Transceiver word Alignment / dual channel in Cyclone V

Hi,

Thanks for your update. As I understand it, you have enable the internal serial loopback but still observe incorrect value at the RX data output. with serial loopback, we can isolate out signal integrity related issue. Since the sync status is asserted, the word alignment has achieved correct word boundary. As I look at the data, seems like there is 1 bit flipped ie 51 vs 53. This is something not expected under serial loopback condition.

If I understand it correctly, you are using signaltap to monitor the data. One of the possible causes to this might be timing problem with signaltap. Can you try the following:

1. Increase the sampling clock of the signaltap to see if it helps. Ideally you should try to increase the sampling clock to at least 2x of the parallel data frequency.

2. Create a design with only single channel. Repeat the test to see if there is any difference?

3. Can you send constant data ie 0xBC51 to see if there is any difference?

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin