Forum Discussion
HBhat2
Contributor
ContributorTransceiver speed grades
Hi, Targeting to use Stratix 10 SX SoC FPGA for an application which includes transceiver working at ~22Gbps per channel. Such 4 to 8 lanes (both TX and Rx) may be there in use at a time. Initially...
CheepinC_altera
Regular Contributor
Regular ContributorHi HPB,
Regarding your inquiry on the documentation in another thread "hat are the exact definitions of chip-to-chip, chip-to-module and back-plane applications?", it seems like I am unable to post to that thread. Thus, I am adding my response to your latest inquiry here for your visibility. Sorry for the inconvenience.
As I searched through the existing documentation ie handbook and user guide, seems like I am unable to locate any specific document which explain in further details on the definition of the interconnect interfaces. I think you might want to search in web to see if you could find any detailed description as reference. Sorry for the inconvenience.
Best regards,
Chee Pin
