Forum Discussion
CStoe2
New Contributor
New ContributorTransceiver in Cyclone V using less then 614 Mbps
Hi all, In a recent project I would like to use a camera with a clock of 290 MHz when using Double Data Rate. The throughput rate is therefore 580 Mbps per channel for a total of 10 channels. Now i...
CStoe2New Contributor
New ContributorHi Chee,
Finally, I changed the FPGA desgin a bit to get it more stable. Since the data source in this case is a camera, I will successively increase the frame rates and resolutions and check up to which configuration the FPGA design works. I will not use the PLL for now, but keep it in mind. The information that the deserializers do not work for this case answers my primary question. Thanks for the support.
Best regards,
Christian
