Topic: how shift in(16 bit) and shift out(1 bit at a time)

wouldn't it be easier to just write something in verilog rather than using a megafunction? i.e.

reg [15:0] bits;

assign shift_out = bits[15];

always @ ( posedge clk )

if ( load )

bits <= data;

else if ( enable )

bits <= { bits[14:0], 1'b0 }; // or bits <= bits << 1, whichever you prefer.

-Mux