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Honored Contributor
Honored ContributorTo build a FIFO using SRAM
Hi, I would like to build a DCFIFO using a SRAM chip on DE2-115. Any idea on where i should start? I know SRAM reads and writes on a different clock cycle as the dataIn and dataOut share t...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Answering my own question... Back to Back means the second data is write to the SRAM right after the first data is wrote to the SRAM. .. i think --- Quote End --- Yes, that is correct. The back-to-back writes still have to satisfy the 0ns setup and hold timing requirements, so you still need to have a clock with write enable high at either end of the write, i.e., two clocks with write enable high between back-to-back writes. Cheers, Dave
