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Honored Contributor
Honored ContributorTo build a FIFO using SRAM
Hi, I would like to build a DCFIFO using a SRAM chip on DE2-115. Any idea on where i should start? I know SRAM reads and writes on a different clock cycle as the dataIn and dataOut share t...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- I really have 0 experience on this... i thought SRAM is suppose to be easy.. at least easier than DRAM. Does anyone have some kinda tutorial i can go through on SRAM? i never learn anything about timing analysis, timing contraints... nothing on timing stuffs, only functional, now i know how important it is. --- Quote End --- Read the TimeQuest guide written by Rysc on the Altera wiki: http://www.alterawiki.com/wiki/timequest_user_guide I have some questions for Rysc related to asynchronous interface TimeQuest constraints. I'm putting those questions into a document dealing with SRAM constraints as the example. I'll post that in a day or so when I get it done (the figure above will be in it). Cheers, Dave
