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Honored Contributor
Honored ContributorTo build a FIFO using SRAM
Hi, I would like to build a DCFIFO using a SRAM chip on DE2-115. Any idea on where i should start? I know SRAM reads and writes on a different clock cycle as the dataIn and dataOut share t...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- If i am using NIOS 2 to control my SRAM, do i need to concern about all of these timing issues? isn't all these be taken care of? --- Quote End --- The tools only do what you tell them. If you do not put in timing constraints, then the tool will happily not apply them. You need to apply appropriate timing constraints to the SRAM interface, or check that the IP core you use includes a TimeQuest .sdc file that applies the appropriate constraints. Cheers, Dave
