timing constraints for EHPI DSP to FPGA asynchronous interface

:) Hello Rysc,

thanks for your reply....one insight that comes up with your analysis is that ...in my case of a strobed external interface.....the launch / latch clock relationships are:

1) FPGA clock on the register which clocks in the data HAD_REG a clock before the strobe is generated

2) Latch clock for HAD data bus is hds_n (rising edge) ....

3) FPGA clock on the register which clocks in the data HCTRL_REG bits a clock before the strobe is generated

4) Latch clock for HAD data bus is has_n (falling edge) ....

There appears to be a multicycle constaint here...the HAD_REG and HCTRL_REG are both clocked in by the fSM a couple of clocks before either of the strobes is generated (again by the FSM).

On the READ side (FPGA reads from DSP) the lauch clock is a DSP internal clock, which generates a DSP_READY flag to the FPGA...the latch clock is the hds_n signal, driven by the FPGA FSM after it detects the DSP_READY flag has gone high.

So on the FPGA to DSP side i think these constraints should be OK:

a) using DSP_TSu and FPGA_to_DSP_Delay_Max (estimated board delays) :

set_output_delay -max [expr DSP_TSu + FPGA_to_DSP_Delay_Max]

This is the FPGA to DSP setup requirement

b) using DSP_Th and FPGA_to_DSP_Delay_Min (estimated board delays) :

set_output_delay -min [expr DSP_TSu + FPGA_to_DSP_Delay_Min]

This is the FPGA to DSP hold requirement

For the DSP to FPGA path:

c) set_input_delay -max = DSP_Tco_max + FPGA_to_DSP_Delay_Max

d) set_input_delay -min = DSP_Tco_min + FPGA_to_DSP_Delay_Min

BUT i dont see now how or why i would also need to use a set_max_delay or set_mn_delay constraint...as you implied here:

If you then apply a set_max_delay, the launch edge will become 0, the latch edge will become the -max value, but the oExt from your set_output_delay will be used. So you could use the set_output_delay to say what the Tsu of the external device is, and then use set_max_delay like you are now. (You could also just tighten your set_max_delay constraint by the Tsu amount and get the same results).

cheers