timing constraints for EHPI DSP to FPGA asynchronous interface

Note that set_input/output_delay and set_max_delay/set_min_delay work together. For example, if you do a set_output_delay assignment to an I/O, there will be three numbers from your .sdc, the launch edge, the latch edge, and the oExt delay. The launch and latch come from the clock relationships, while oExt comes directly from the -max and -min values. If you then apply a set_max_delay, the launch edge will become 0, the latch edge will become the -max value, but the oExt from your set_output_delay will be used. So you could use the set_output_delay to say what the Tsu of the external device is, and then use set_max_delay like you are now. (You could also just tighten your set_max_delay constraint by the Tsu amount and get the same results).