timing constraints for EHPI DSP to FPGA asynchronous interface

You can invert a generated clock with -invert.

In reality, that's probably not correct, as it's not really inverted. You could also add -clock_fall to your set_output_delay and it would know it's latching on the falling edge. (The two solutions should give the same analysis in the end). Some other quick thoughts:

- I was thinking of still using set_output_delay for the address/data outputs, since the strobes act a lot like a clock. In that case, you don't really have to constrain the strobes themselves, since the data will be constrained in relation to them. What you have now is more of a "I know the strobes will get out between a-b times, and so my data needs to get out between x-y times plus the clock cycle in my desgin..."

Note that inverting the output clock doesn't matter if you don't use it(which you're not with set_max_delay), and that even if you did, set_max_delay would ignore that inversion since set_max_delay overrides the calculated setup relationship.