timing constraints for EHPI DSP to FPGA asynchronous interface

Your well on your way. I spend a lot of time looking at the report_timing results. Note that report_timing -setup generally has only two numbers that come from your .sdc, the setup relationship and the external delay(oExt or iExt). The external delays are pulled directly from your -max/-min values. The setup relationship comes from your clock descriptions and multicycles. For now, ignore whether it meets timing or not, and just look at those two values and see if they're what you want. Same goes for hold. If your constraints are correct, THEN look at why it's failing. (And remember that you may have to re-compile once they're correct, as the place-and-route you're looking at is based on incorrect constraints). Good luck.