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Altera_Forum
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15 years ago

timing constraints for EHPI DSP to FPGA asynchronous interface

Hi, I am trying to write timing constraints for connecting a TI DSP, TMS320VC5510A, to a Cyclone IV FPGA. The bus used is EHPI in Multiplexed mode. It looks confusing because the interface is asynchr...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Is it a top-level register? I would normally assume there is a hierarchy path to it. (Note that I recommend get_keepers over get_registers. Either should work, but get_registers isn't a true .sdc command and was added by Altera, where get_keepers is more standardized). In TimeQuest go to View -> Name Finder and use that try and whittle down why it isn't matching. Or go to the Technology Map viewer and look for it there. There's a chance it got synthesized out or something, but most likely it's just a name matching issue. Another thought is to run:

report_path -to [get_ports hds_n] -panel_name test

and see what is driving it.