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Altera_Forum
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14 years ago

timing constraints for EHPI DSP to FPGA asynchronous interface

Hi, I am trying to write timing constraints for connecting a TI DSP, TMS320VC5510A, to a Cyclone IV FPGA. The bus used is EHPI in Multiplexed mode. It looks confusing because the interface is asynchr...
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Altera_Forum
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14 years ago

Hi Rysc....i'm getting there (I think !)....but i see this warning during project compilation fro Quartus:

Warning: Ignored filter at AlteraIOTiming_Strobed_TestProject.sdc(35): hds_ni could not be matched with a register

# Create Generated Clock for STROBE from PLL driving REG

create_generated_clock -name HAD_STROBE_REG -source EHPI_PLL_inst|altpll_component|auto_generated|pll1|clk[0] [get_registers hds_ni]

Even though hds_ni is a register in my design driving output pin : hds_n

Not sure what is happening here !

cheers