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Honored Contributor
Honored Contributortiming constraints for EHPI DSP to FPGA asynchronous interface
Hi, I am trying to write timing constraints for connecting a TI DSP, TMS320VC5510A, to a Cyclone IV FPGA. The bus used is EHPI in Multiplexed mode. It looks confusing because the interface is asynchr...
Altera_ForumHonored Contributor
Honored ContributorLooks correct. Look at the messages when reading in the .sdc and updating the netlist. I'm guessing there's a warning or two.
