timing constraints for EHPI DSP to FPGA asynchronous interface

Are your generated clocks working? I see a space in the -source clock name, which would break it, and I don't see it applied to anything. I would expect something like:

create_generated_clock -name HAS_STROBE -source EHPI_PLL_inst|altpll_component|auto_generated|pll1|clk[0] [get_ports HAS_STROBE]

(I don't know the name of the port, but guessing HAS_STROBE)

If the generated clock isn't correct, then it all falls apart and I would expect it to not have any timing, since you use those clocks for the rest of the design.

Does the PLL drive the strobes directly, or does it drive a register that drives the strobe? If the latter, you need to put a generated clock on the register from the PLL, and then one on the output port where the source is the register.

When you run

report_timing -setup -npaths 100 -detail full_path -to_clock HAS_STROBE -panel_name "HAS_STROBE||setup"

report_timing -hold -npaths 100 -detail full_path -to_clock HAS_STROBE -panel_name "HAS_STROBE||hold"

Make sure the data required path shows the entire clock path from inclk0, through the PLL, through the register(if there is one) and out the port. If it doesn't, that needs to be fixed before worrying about multicycles and what values for -min/-max.