timing constraints for EHPI DSP to FPGA asynchronous interface

Hi Rysc...what might prove rally helpfull to me would be an example in SDC syntax of constraining a simple sort of async interface ....such as what constraints to apply to the HAD I/O bus (which is Tristatable), how to create the clocks (HAS and HDS) based on the strobes....i assume i would create a couple of Virtual clocks here.....and what sort of MC constrainst i need ?