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Honored Contributor
Honored ContributorTiming constraints for 2 clocks, phase shifted by 90 degrees
Hello all, I have a design, in which two clocks are used. One main clock and another one with 90 degree fixed phase shift. There are registers that are related to these clocks, for example re...
Altera_ForumHonored Contributor
Honored ContributorAssuming both clocks are coming from a PLL, first create your base (reference) clock into the device. Then use derive_pll_clocks to create the clock constraints. If you're not using a PLL, you'll need to use create_generated_clock in your .sdc file. See these online trainings for details:
https://www.altera.com/support/training/catalog.html?coursetype=online&language=english&keywords=timing (If URL doesn't work, put "timing" or "timing analyzer" in the filter.)
