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Altera_Forum
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13 years ago

TimeQuest reporting paths between multiple LPM Divides

Hi, I'm using the latest version of Quartus (12.1 with sp1) and a number of LPM dividers in a Cyclone 3 FPGA design (plus other LPMs, RAMs, PLLs, VHDL modules, etc.,). The dividers in question...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Rather reminds me of a laptop pcb. Some of the instabilities were finally found to be caused by the parallel port parity and the cpu bus parity being connected together because they'd been given the same name! can't have helped the board routing either.